1. Field of the Invention
In data transmission technology there is a general need for extracting a clock from a data stream. A data transmission standard which recently spread increasingly is the USB standard (USB=universal serial bus). The USB standard standardizes a data transmission format for a fast data transmission between USB devices and a host. The USB standard defines a so-called tier-star-topology, wherein USB devices may either be hubs or functions or functional devices, respectively. The USB data format is specified in the USB specification. The most current USB definition is currently USB revision 2.0.
2. Description of the Related Art
The USB bus is a semi-duplex bus. All transactions are initiated by the host. In the USB specification revision 2.0 three data transmission rates are defined. The lowest data transmission rate is used in the low-speed mode and comprises 1.5 megabits per second. In the full-speed mode a data transmission rate of 12 megabits per second is used. In the high-speed mode a data transmission rate of 480 megabits per second is used.
The use of the low-speed mode serves for interactive devices, like e.g. a keyboard or a mouse. Only a limited number of low-speed devices should be connected to the bus in order to prevent a degradation of the bus efficiency. For full-speed and high-speed devices a special bandwidth and latency are guaranteed.
Devices are connected to the USB bus via a 4-wire cable, carrying differential data, a power signal and mass. This means, that one core of the 4-wire cables carries a positive differential signal Dp, that a further core of the 4-wire cables carries a negative differential signal Dn and that a further core is on the supply potential and that finally the last core is on the mass potential. The clock information is encoded in the data. According to the USB specification an NRZI encoding and a bit stuffing technology are used in order to guarantee an adequate number of transitions. NRZI means no return to zero invert. This means, that an inverse encoding is used. A logical “1” signal is represented by a non-present change in an electrical signal, while a logical “0” signal is represented by a change of state of the electrical signal. One edge thus represents a zero, while a non-present change, i.e. a steady-state signal, represents a zero. Further, for a steady component reduction a bit stuffing is used, so that after six subsequent ones a positive/negative edge is used.
As it is illustrated in FIG. 7b, the data stream is defined as a series of frames 72, 73, which are separated from each other by so-called control characters 74, wherein the ticks occur at an interval of 1 ms. Within the frame 72 or 73 a plurality of data packets is located. This means that a frame consists of several data packets and that a data stream consists of a plurality of subsequent frames. Each data packet is introduced in the data stream by a packet identification number having a width of 8 bits and illustrated in FIG. 7c. One frame thus includes as many packet identification numbers (PID) as there are packets in the frame. The specification of the packet identification number illustrated in FIG. 7c which is four bits wide and presented in a PID field by the four PID bits PID0, PID1, PID2, PID3 and by the correspondingly inverted PID bits, is determined in the USB standard. The bits represented in FIG. 7c are arranged from the LSb to the MSb. LSb stands for least significant bit, while MSb stands for most significant bit.
The host transmits a start of frame packet (SOF packet) once per millisecond in order to define the ticks 74 represented in FIG. 7b. The SOF packet is represented in FIG. 7d and includes an SYNC field (not illustrated in FIG. 7d), an SOF-PID field 75, an 11-bit frame number (76) and a CRC check sum for the field 76 which is entered into a field 77. The frame number 76 is incremented by 1 with every additional SOF packet.
In FIG. 7a, for example, the synchronization pattern (SYNC pattern) preceding the PID field 75 of FIG. 7d is illustrated as an electric signal. It consists of a sequence of bits specified in the USB standard or of a data pattern, respectively, that looks as illustrated in FIG. 7a as an electric signal due to the NRZI encoding. The sequence of databits is 00000001, which leads to the “electric” sequence 10101011 shown in FIG. 7a. Before the synchronization data pattern an area designated by idle is located comprising with regard to the differential signals Dp and Dm a single-ended zero encoding (SE0 encoding), as it is discussed in the following. This SE0 encoding of the Dp and Dm signals indicates the end of the preceding frame and further indicates that now a new frame follows that is introduced by a synchronization field and is directly followed, as it is shown in FIG. 7a, by the packet identification number and in particular, as it is shown in FIG. 7c, a least significant bit of the PID and the next high-order bit of the PID, etc.
The notation shown in FIG. 7a illustrates that the bits are fixed in the synchronization pattern and that the associated electric signal can have the sequence of 10101011, while the PID bits may have both a 0 or a 1, depending on the packet identification to be encoded.
Every low-speed or full-speed data packet transmitted via the USB bus thus starts with a synchronization pattern (FIG. 7a) followed by the packet identification number (PID), as illustrated in FIG. 7c, which defines the packet type. The synchronization field includes a series of 0-1 transitions on the bus in order to enable a receiver to synchronize onto the bit clock.
As it is illustrated in FIG. 7, a frame interval of one millisecond is defined. The host transmits an SOF packet (start of frame packet) once per millisecond (FIG. 7b). The SOF packet consists of a synchronization field followed by the SOF-PID, an 11-bit frame number and a CRC 5-finger print (FIG. 7d). The frame number is incremented with every SOF packet sent.
When a device is connected to the USB bus, a startup sequence takes place. At the end of this sequence the device is driven into a reset state. After the reset event the device has a time period of 10 milliseconds in order to perform a reset recovery. During this time the device receives SOF packets.
A conventional USB device is schematically illustrated in FIG. 9. It includes an analog USB front end that may be integrated with a differential transmitter (TX) and a differential receiver (RX) in a functional unit 90. At one side of the element 90 the signals Dp and Dm are present in analog form, while at another side of the element 90 the corresponding received and analog/digital-converted signals are applied that are fed into a USB core 91 or are received from the same, respectively. These signals are illustrated in FIG. 9 by the two pairs of parallel signal arrows. The USB device further includes a crystal oscillator 92 connected to a crystal oscillator wiring 93, wherein the crystal oscillator wiring 93 on the one hand controls the USB core 91 and on the other hand a clock distribution 94 connected to a CPU 95 which is again in operational connection with a memory 96. Further, a USB device, depending on the application, also includes a parallel input/output interface (parallel I/O) 97.
Such conventional USB devices typically use a crystal oscillator 92 as a clock source for the system devices and the USB data recovery circuit, as it may be seen from FIG. 9. For robust portable devices, like e.g. chip cards, it would be desirable that they extract their own local clock directly from the USB data stream. For such devices the use of crystal oscillators is impractical, as crystals may usually not be integrated into a chip and are further very prone to damage due to mechanical loads. Chip cards are usually carried in rough environments, like e.g. in a purse carried in a trouser pocket. The thus exerted mechanical load would be fatal for a quartz crystal oscillator.
Thus, clock generation circuits for USB devices which were developed in the low-speed mode do not require crystal oscillators.
US 2001/0011914 A1 discloses a device for the recovery of a clock signal from at least two synchronization bits. As a reference clock signal a signal of an internal oscillator is used in order to measure the number of reference clock pulses between the first two synchronization pulses sent from one external USB bus at the beginning of each transaction. Thus, a coarse measurement N for the USB clock signal is obtained which is to be regenerated. The delay of each of these two synchronization pulses with regard to the preceding pulse of the reference clock signal is measured. This delay is calculated with regard to an internally defined time unit. On the basis of the measurement of these two delays and the measurement of a number of reference clock periods.
US 2001/0020857 A1 discloses a device for the regeneration of a clock signal from an external serial bus, wherein the device comprises a ring oscillator and a counter. The ring oscillator provides n phases of a clock signal. Of those n phases one phase is used as a reference and applied to the counter. It is thus possible to count the number of overall reference clock signal periods between a first pulse and a second pulse which are obtained from the bus. When reading the state of the phases in the oscillator when receiving the second pulse a current phase is determined corresponding to the phase shift between the reference clock signal and the second pulse of the bus. Using a regeneration device also including a ring oscillator and a counter, it is possible to regenerate the clock signal on the bus with a high accuracy.
The U.S. Pat. No. 6,343,364 B1 discloses a method and a device for a local clock generation using the USB signals Dp and Dm operating without a quartz crystal oscillator or a resonator. For this, a number of cycles of a free-running high-frequency clock signal are counted occurring in a known number of bit periods of the received signal. Hereupon, the counted number of cycles of the free-running high-frequency signal is separated by the known number of bit periods in order to determine a resulting number of clock cycles contained in a single bit duration of the received USB signal. Based on this, a local clock signal is generated.
WO 00/16255 discloses a method for data transmission and a smart card suitable for this. The signals Dp and Dm are connected to an interface of the card. The card further includes a CPU, memory units, USB output contacts and an arrangement of at least six contact faces level with the surface of the card body.
The U.S. Pat. No. 5,487,084 discloses a concept for generating a clock frequency in a smart card interface used for a data transmission from a smart card for example to a mobile telephone in order to obtain a predetermined data rate. A phase-locked loop and a number of programmable counters are used in order to obtain a clock signal with a frequency which is a multiple of the data rate. In particular, the counters and the phase-locked loop may be selected so that the frequency is the 16-fold of such a data rate to be able to use a universal asynchronous receiver/transmitter (UART).
The U.S. Pat. No. 5,818,948 discloses an architecture for a USB-based PC loudspeaker control device. For recovering a clock from the received data stream a phase-locked loop is used.
The U.S. Pat. No. 6,061,802 discloses a software-based clock synchronization with an isochronous master clock structure in which the frame rate clocks of a plurality of data busses are synchronized onto a master clock signal. The master clock signal is derived from the existing clock signals within the computer system or from data received from an external source.
The U.S. Pat. No. 6,092,210 discloses a device and a method for synchronizing the clocks of connected USB busses by synchronizing clocks in a local device to the data streams of both USB busses. For this, a separate local clock synchronization device for each USB device is used connected to the regarded USB device. Every separated local clock synchronization may use the same reference clock.
DE 10041772 C2 discloses a clock generator, in particular for USB devices, wherein due to a synchronization signal periodically returning in the data stream a pulse filter is controlled in order to reduce a frequency of a pulse train output by an internal block generator by suppressing pulses in the effective frequency. Further, using the synchronization signal and a value stored in a pulse number storage or using an output signal of a data signal decoder, respectively, a frequency generated by the internal clock generator is re-tuned.
Conventional clock recovery systems, as they are presented in the above-described references, use the synchronization pattern (FIG. 7a) preceding every USB data packet. This may be sufficient for low-speed USB applications with regard to accuracy. For faster applications in the USB full-speed mode or the USB high-speed mode the accuracy of the synchronization pattern is too low. This is illustrated with regard to the following numerical examples. There is a requirement for full-speed USB devices in so far that the transmission clock must be accurate to 0.25% (2500 ppm). Due to the large time jitter which is at 12 ns for paired transitions or at 20 ns for consecutive transitions, respectively, admitted for the serial bit data on the USB bus, a reliable clock recovery merely based on the synchronization pattern is not possible.